Modern semiconductor based integrated circuits (ICs) are incredibly complex and contain millions of circuit devices, such as transistors, and millions of interconnections between the circuit devices. Designing, testing, and verifying the functionality of such complex circuits cannot be accomplished manually, and circuit designers use computer based Electronic Design Automation (EDA) tools for schematics, layouts, simulation, and verification of the complex circuits. In additional to designing an IC with the correct functionality, another equally significant function of the EDA tools is to optimize the IC design. One of the optimization targets is to reduce power consumption by the fabricated IC. In addition to consuming less power and offering a longer battery life, an IC with reduced power consumption generates less heat and does not require elaborate heat dissipation mechanism. In this age of portable and yet incredibly complex electronics, ICs with reduced power consumption have therefore been increasingly relevant and sought after.
To allow a circuit designer to optimize power consumption, EDA tools offer power consumption verification of an IC design. Conventional EDA tools generally use vector-based power analysis, in which an IC design is simulated by feeding a test vector of inputs. The simulation then generates value change dump (VCD) files based on the simulation. The VCD files can be parsed to determine the current flow through circuit instances in the IC design. The current flow can be then used to calculate the power consumed by the circuit instances. However, as the complexity of ICs has been increasing exponentially, vector-based power analysis has become computationally expensive as the entire IC has to be simulated for multiple clock-cycles to generate the VCD files. Furthermore, significant computation resources have to be expended to parse the generated VCD files, determine the current flowing through various circuit instances, and calculate the power consumed by the IC.
Vectorless power analysis, which may heuristically model the transient power consumption for both sequential and combinational circuit devices in an IC design, may be more computationally efficient than a VCD based power analysis. However, conventional vectorless power analysis technology may not be accurate for IC designs including multiple clock domains. For example, FIGS. 1A and 1B show the inaccuracies when a conventional vectorless power analysis technology is used in an IC design that includes multiple clock domains. In FIG. 1A, the dominant clock signal 101 has a frequency of 2 GHz, faster than the frequency (1 GHz) of an instance clock signal 102 for a sequential circuit device. As shown herein, if a scheduling cycle includes two rising edges 107a, 107b of the dominant clock signal 101, then two rising edges 103a, 103b for the instance clock signal 102 may be scheduled as well. However, the instance clock signal 102 has one rising edge 103a for the scheduling cycle and the conventional vectorless power analysis technology toggles twice the state of the sequential circuit device driven by the instance clock signal 102 thereby generating a pessimistic power analysis result. In FIG. 1B, the dominant clock signal 104 has a frequency of 1 GHz and is slower than an instance clock signal 105 with a frequency of the 2 GHz. A scheduling cycle includes two rising edges 108a, 108b of the dominant clock signal 104. However, the scheduling cycle includes four rising edges 106a, 106b, 106c, 106d of the instance clock signal 105. In a conventional vectorless power analysis, only the first two rising edges 106a, 106b may be scheduled, thereby generating an overly optimistic power analysis result. In both instances, the power analysis result is inaccurate: in the first instance, the power consumption is shown to inaccurately higher, and in the second instance, the power consumption is shown to be inaccurately lower.